Pevita Pearce
In a significant development for the semiconductor industry, researchers at the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) have announced the successful fabrication of experimental stacked-nanosheet gate-all-around (GAA) transistors. This breakthrough, achieved using immersion deep-ultraviolet (DUV) lithography, represents a strategic pivot for China’s domestic semiconductor industry, which continues to face stringent export controls preventing access to high-end extreme ultraviolet (EUV) lithography systems.
While the scientific achievement is notable, industry analysts remain cautious regarding its commercial viability. The demonstration proves that the fundamental architecture of 3nm-class nodes can be approached without the industry-standard EUV equipment, yet the leap from a laboratory test chip to a high-yield, mass-production environment remains a formidable technical chasm.
Main Facts: The GAA Transition and DUV Limitations
The semiconductor industry is currently in the midst of a generational shift in transistor architecture. As traditional FinFET (Fin Field-Effect Transistor) designs reach their physical limits at smaller nodes, manufacturers are transitioning to Gate-All-Around (GAA) nanosheet structures. GAA designs allow for better electrostatic control over the transistor channel, reducing leakage and enabling higher performance at lower power consumption.
IMECAS’s experimental process flow leverages immersion DUV lithography—a technology that utilizes 193nm light—to pattern features that are technically smaller than the wavelength of the light itself. This is achieved through complex multi-patterning techniques and self-aligned processes. By stacking nanosheets, IMECAS aims to provide a pathway for Chinese foundries to reach the 3nm node and beyond, effectively bypassing the need for the ASML-manufactured EUV scanners that currently serve as the gold standard for sub-7nm manufacturing.
However, the "functional device" reported is not a mass-production ready chip. It is an experimental proof-of-concept. The process flow developed by the institute is currently a methodology for research-level fabrication, lacking the robustness, thermal budget management, and defect density control required for commercial logic chips.
Chronology: The Road to Domestic Sovereignty
The pursuit of advanced nodes without EUV is the culmination of several years of intensified research within the Chinese state-backed ecosystem.
- 2019–2020: The intensification of U.S. export controls limits the ability of Chinese firms like SMIC to acquire EUV scanners. The domestic research agenda shifts focus toward maximizing the potential of existing DUV infrastructure.
- 2021–2022: IMECAS and other research bodies begin publishing papers on "multi-patterning" and "self-aligned quadruple patterning" (SAQP), aiming to push DUV lithography to its theoretical limits.
- 2023: Early reports surface regarding Chinese research into nanosheet architectures. The scientific community begins to debate whether "EUV-less" 3nm is physically possible, given the extreme complexity of nanosheet patterning.
- September 2026: IMECAS confirms the successful fabrication of stacked-nanosheet GAA transistors. This serves as a watershed moment, proving that the structural architecture is achievable in a lab setting without EUV light sources.
Supporting Data: Understanding the Physics and Scale
To understand the magnitude of this challenge, one must look at the geometric constraints. A 3nm-class transistor requires a gate pitch and metal pitch that are notoriously difficult to resolve with 193nm DUV light.
The EUV vs. DUV Divide
EUV lithography (13.5nm wavelength) simplifies the manufacturing of 3nm transistors by reducing the number of patterning steps. DUV lithography, by contrast, requires aggressive multi-patterning. If a standard 3nm layer requires two or three EUV masks, the same layer might require ten or more DUV masks. This leads to:
- Overlay Error: Every additional mask layer introduces a risk of misalignment, which can ruin the functional integrity of the transistor.
- Yield Degradation: More steps increase the time in the cleanroom and the statistical probability of a fatal defect occurring on the wafer.
- Cost Escalation: While the tool is cheaper than an EUV scanner, the throughput is lower and the operational cost of multi-patterning is exponentially higher.
IMECAS has not yet disclosed the specific geometrical parameters (such as nanosheet width, height, or gate length) of their device. Without this data, industry analysts cannot confirm whether these transistors meet the performance-per-watt metrics required for 3nm designation. In the industry, a "3nm" label is often a marketing term; true 3nm performance depends on the density of the transistors and the specific mobility of the carriers within the nanosheets.
Official Responses and Industry Outlook
The response from the global semiconductor community has been one of professional curiosity tempered by skepticism.
The Academic Perspective:
Researchers within the Chinese Academy of Sciences emphasize that the goal was to prove the feasibility of the "GAA architecture under DUV constraints." Their response highlights that they have overcome the initial hurdles of material selection and channel release—the process of etching away sacrificial layers to leave behind the free-standing nanosheets.
The Industry Perspective:
Foundry executives and market analysts have noted that the gap between a research device and a production-grade chip is vast. A source familiar with the development noted, "Building a transistor is a triumph of physics; building a billion transistors on a single die with a 90% yield is a triumph of manufacturing engineering."
The industry remains focused on whether IMECAS can provide a clear pathway for commercialization. Without a defined "process flow" for mass production, companies like SMIC are unlikely to adopt this specific methodology in the near term, preferring to wait for further refinement of the process stability.
Implications: A Shifting Semiconductor Landscape
The IMECAS breakthrough has profound implications for the global geopolitical landscape of technology.
1. Resilience Against Sanctions
The most immediate implication is a shift in the perceived efficacy of technology blockades. By demonstrating that 3nm-class architectures can be approached without EUV, China is signaling that while its progress may be slowed or made more expensive by export controls, it is not halted. This encourages domestic investment into the entire supply chain, from photoresists to DUV light sources.
2. The Cost of "EUV-Less" Innovation
There is a trade-off. If China manages to scale this process to high-volume manufacturing, the resulting chips will likely be more expensive to produce than those manufactured using EUV. This creates a "sovereignty premium"—the cost that the Chinese government and consumer market must pay to utilize chips that are independent of Western supply chains.
3. The Future of Lithography
This development may force a re-evaluation of the "EUV-essential" paradigm. While EUV remains the most efficient path forward, the engineering community may now be incentivized to look for more creative, non-EUV methods to achieve miniaturization. This could lead to advancements in self-assembly, directed energy deposition, or alternative nanostructure architectures that do not rely solely on optical resolution limits.
4. A New Arms Race in Packaging
Since the transistor architecture is only half the battle, the implications for advanced packaging (Chiplets, 3D stacking) are significant. If individual transistors are harder to shrink, the industry will focus even more on connecting larger chips together efficiently. We can expect China to double down on CoWoS (Chip-on-Wafer-on-Substrate) and other advanced packaging technologies to compensate for any remaining density gaps.
Conclusion
The successful demonstration of GAA nanosheet transistors by IMECAS using DUV lithography is a landmark achievement in materials science and process engineering. It confirms that the physical architecture of next-generation semiconductors is accessible even to those restricted from the most advanced lithographic tools.
However, the journey from a laboratory testbed to the silicon in a smartphone or an AI server is measured in years of yield optimization, equipment calibration, and infrastructure development. Whether this technology will serve as a viable alternative for Chinese chipmakers in the 3nm era remains an open question. For now, the global industry watches with bated breath, recognizing that while the "EUV barrier" has not been broken, it has, for the first time, been significantly challenged. The landscape of 2030, once thought to be exclusively defined by EUV-based nodes, now looks considerably more complex and competitive.
Nana Muazin
