Layla Zulfa
By [Your Name/Staff Writer]
Reporting from Hot Chips 2026, Cupertino
The evolution of High Bandwidth Memory (HBM) has become the defining bottleneck—and the primary catalyst—for the modern artificial intelligence era. As the demand for larger, faster, and more efficient AI accelerators pushes the limits of silicon manufacturing, the industry’s major players are locked in an intense race to optimize memory packaging. However, during a pivotal presentation at the Hot Chips 2026 conference on August 23, Jaesik Lee, Vice President of Package Engineering at SK Hynix America, provided a sobering reality check regarding the timeline for the industry’s most anticipated transition: hybrid bonding.
Contrary to widespread industry speculation, SK Hynix has signaled that hybrid bonding will not be ready for the upcoming HBM4E generation. Instead, the company is doubling down on its refined Mass Reflow-Molded Underfill (MR-MUF) process, effectively pushing the adoption of copper-to-copper hybrid bonding to HBM5 at the earliest.
Main Facts: The 775-Micron Reality
The central challenge facing memory engineers today is a fundamental physical constraint: the total thickness of the HBM stack. For current-generation accelerators, the industry is capped at a height of 775 microns—the standard thickness of a 300mm logic wafer. This limit is non-negotiable because the memory stack must sit flush with the GPU/NPU die when the cold plate is attached for thermal management.
"That’s the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns," Lee explained.
As SK Hynix scales its 16-high (16-Hi) HBM4 stacks, which offer a massive 48GB capacity per cube, the physical margins have vanished. To fit 16 layers of DRAM into that 775-micron envelope, engineers have been forced to thin the core dies to approximately 50 microns each, while simultaneously halving the gap between the dies. This creates a cascade of secondary problems: as dies become thinner, the proportion of oxide within the stack increases. Since oxide is a poor conductor of heat compared to silicon, the thermal resistance of these high-density stacks is rising rapidly.
Chronology of an Evolving Standard
The trajectory of HBM packaging has been a series of tactical shifts designed to buy time for next-generation manufacturing technologies.
- HBM3E Era: The industry relied on a 720-micron package height ceiling, utilizing standard MR-MUF processes that have proven reliable for years.
- The HBM4 Shift (2025–2026): JEDEC, the body responsible for memory standards, officially raised the ceiling to 775 microns. This move provided the necessary breathing room for 16-Hi HBM4 to reach market-ready status without needing to switch to the more complex hybrid bonding process.
- The Future (2027–2030): Industry discourse is already shifting toward 20-Hi stacks. Current discussions suggest a further increase in the thickness limit to between 825 and 900 microns. This shift would once again delay the "forced" adoption of hybrid bonding, as it allows manufacturers to stick with the proven MR-MUF process for a while longer.
While Samsung publicly committed to hybrid bonding for HBM4 as early as May 2025, SK Hynix has maintained a more conservative stance, keeping hybrid bonding as a high-end "backup" while optimizing its proprietary MR-MUF. With the HBM4 generation now in customer qualification, it is clear that SK Hynix has prioritized manufacturing yield and stability over the immediate adoption of the more exotic copper-to-copper technique.
Supporting Data: The Thermal and Physical Burden
The technical data presented by Lee paints a stark picture of the challenges ahead. As pin speeds have escalated from a modest 1 Gbps in the early days of HBM to 8 Gbps in the HBM4 generation, the power density has skyrocketed.
SK Hynix’s internal metrics indicate that the thermal burden—the amount of heat generated per unit of surface area—is now 2.2 times higher than it was just a few generations ago. Simultaneously, the stack counts are doubling every two years. Managing this requires incredible precision; the company’s current MR-MUF process involves a delicate pick-and-place operation followed by a single reflow phase. Controlling the warpage of sub-50-micron dies during this process is, according to Lee, "the main manufacturing challenge of 16-Hi."
Regarding the move to hybrid bonding, the benefits are clear on paper, even if the implementation is daunting. By removing the need for micro-bumps entirely, core dies can be up to 24% thicker in a 20-Hi stack. This reduction in complexity also cuts thermal resistance by roughly 35% compared to MR-MUF, and allows the bump pitch to shrink below 18 microns—a significant improvement over the 30-micron pitch standard for current MR-MUF processes.
Official Responses and Strategic Directions
A significant portion of the Hot Chips session was dedicated to the "iHBM" cooling architecture. Unveiled initially in May 2026, the technology embeds thermally conductive, electrically insulating blocks directly into the base die’s die-to-die (D2D) PHY region—the specific area where heat generation is most intense.
SK Hynix claims this architecture cuts thermal resistance by more than 30%. However, Lee was careful to manage expectations regarding its rollout. Because these cooling blocks must be integrated into the physical design of the base die, they cannot be "bolted on" to existing designs. "It’s a kind of good option that we can do, but this is not something that we can apply to the generation that we already have in design," Lee noted. Consequently, iHBM is being positioned specifically for next-generation HBM5 accelerators, likely arriving in mass production no earlier than 2028.
The competition is not standing still. Samsung has showcased its own "Heat Path Block" approach, while Micron has focused on a base-die circuit redesign. Each company is effectively attacking the same thermal wall from a different engineering perspective, with all three solutions currently in the development pipeline for the HBM5 era.
Implications: The Question of Efficiency
The most provocative moment of the session occurred during the Q&A, when Tanj Bennett of SemiAnalysis challenged the industry’s obsession with ever-taller stacks. Bennett pointed out that as stacks grow to 20 layers, the average speed of the memory begins to lag behind standard DDR5 due to the complexities of the throughput-per-square-centimeter.
"Why is it better to be using the height of the HBM stack instead of intelligently placing cheaper memory around it?" Bennett asked.
This question touches on a growing consensus in the industry: the future of AI memory may not be a single, monolithic HBM stack, but rather a tiered memory hierarchy. We are already seeing this in practice with platforms like Nvidia’s "Vera Rubin," which pools LPDDR5X with HBM4. The development of the High Bandwidth Flash (HBF) specification, co-developed by SK Hynix and SanDisk, further suggests that the industry is moving toward a future where "Tiered Memory" is the standard.
For SK Hynix, this means balancing its dominance in the HBM market (where it reportedly holds 70% of Nvidia’s current orders) with the need to innovate. The company remains at the forefront of HBM production, but the transition to the next frontier—hybrid bonding—remains a "very simple process in theory, but in reality, it’s really challenging," as Lee admitted.
With 16-Hi HBM4 currently entering mass production, the focus for the next 24 months is clear: refining the existing MR-MUF process to maximize yield, improving cooling through structural innovation, and carefully evaluating when the performance gains of hybrid bonding will finally outweigh the massive engineering risks associated with its implementation. For now, the 775-micron limit remains the iron law of the HBM world, and until that changes, the industry will continue to squeeze every last bit of performance out of the silicon it already knows how to stack.
Nila Kartika Wati
Evan Lee Salim
